Typical radio frequency (RF) transmission/reception occurs at frequencies that are so high that performing signal processing at such frequencies is considered impractical according to the Background Art. As a result, high frequency signals are received and then translated to the lower frequencies for processing, according to the Background Art.
Historically, the super heterodyne receiver has been the receiver architecture widely accepted and implemented commercially according to the Background Art. In the typical super heterodyne receiver, the received high frequency signals are passed through a first radio frequency (RF) bandpass filter (BPF) to a fixed-gain low noise amplifier (LNA). The amplified signals are passed through a second RF BPF to a first mixer that uses a first local oscillator signal for downconverting (translating) to a fixed intermediate frequency (IF). The resultant IF signals are amplified by a variable gain amplifier (VGA) and then provided to parallel second mixers. In-phase and quadrature (90°) phase versions of a second local oscillator are then provided to the parallel second mixers to downconvert the IF signals into in-phase (I) and quadrature phase (Q) baseband signals.
Over the last few years, the direct-conversion type of receiver architecture has become adopted by the wireless telephony art, primarily for use in handsets. In the typical direct-conversion receiver, the received high frequency signals are passed through a first radio frequency (RF) bandpass filter (BPF) to a fixed-gain LNA. The amplified signals are passed through a second RF BPF and then directly down-converted to in-phase (I) and quadrature phase (Q) baseband signals without an intervening IF mixer stage. The I & Q baseband signals are then passed through parallel lowpass filters (LPFs) to parallel VGAs.
Component mismatches, e.g., due to manufacturing tolerances, etc., in the parallel second mixers and/or the parallel VGAs can produce DC offsets in the I & Q baseband signals. As the headroom of the parallel VGAs is typically limited, a small DC offset can significantly reduce the signal swing or possibly saturate the VGAs when they operate in high-gain mode, thus degrading the receiver's effective dynamic range. In other words, such component mismatches can degrade the second order intercept point (IP2) of the receiver. To reduce this problem, the Background Art adaptively compensated for the device mismatches during manufacture of the handsets.
FIG. 6 illustrates a direct-conversion receiver 201, according to the Background Art.
In FIG. 6, receiver 201 includes an integrated circuit (IC) 200 and a second bandpass filtering circuit 205 (for brevity, a corresponding first BPF upstream from LNA 210 is not depicted). Bandpass filtering circuit 205 is external to IC 200. Typical components of bandpass filtering circuit 205, for example, include: a capacitor C1; a surface acoustic wave (SAW) type of bandpass filter; capacitors C2 and C3 connected between the SAW filter and the output nodes (nodes N4 & N6), respectively, of bandpass filtering circuit 205; inductors L1 & L2 connected between nodes N4 & N8 and node N6, respectively; and a capacitor C4 connected between node N8 and ground. The amplified high frequency signals on node N2 are provided to the SAW filter which provides filtered signals to capacitors C1 & C2.
IC 200 of FIG. 6 includes LNA 210, a block 220 representing parallel mixers, a block 230 representing parallel LPFs; a block 240 representing parallel VGAs; and a fuse array 260. During manufacture, a technician 266 uses an instrument 268 to measure the output impedance of mixer 220 and thereby assess the degree to which components of mixer 220 are mismatched. Based upon trial and error, the technician configures a fuse array 260 by which a compensating impedance is introduced that reduces the effect of the mismatched components.